/*****************************************************************************
* File Name          : SIC931_Chip_Function.h
* Author             : Ohmmarin Sathusen
* Version            : V1.5.0.0
* Date               : 18/09/2012
* Description        : 
******************************************************************************/                       

#ifndef SIC931_DEFINE_H__
#define SIC931_DEFINE_H__

/********************************************************************************/

#include <stdint.h>

/******************  Define ASIC Version *******************************/

#define	 ASIC_SIC9310	        0x01
#define	 ASIC_SIC9100	        0x02
#define	 ASIC_SIC9410	        0x03
#define	 ASIC_SIC9311	        0x04
#define	 ASIC_SIC9101	        0x05
#define	 ASIC_Series_9          0x06
#define	 ASIC_Unknown	        0xFF


//************ General Parameter (can edit or config) ******************//
#define	 MAX_ADDR		63
#define	 WaterLevel		16
#define  HiLevel		64 - WaterLevel

//************ Register Setting for DSRC931B **************************//
#define	 RegPage						0x00

#define	 RegCommand						0x01
#define	 RegFIFOData					0x02
#define	 RegPrimaryStatus				0x03
#define	 RegFIFOLength					0x04
#define	 RegSecondaryStatus				0x05
#define	 RegInterruptEn					0x06
#define	 RegInterruptRq					0x07

#define	 RegControl						0x09
#define	 RegErrorFlag					0x0A
#define	 RegCollPos						0x0B
#define	 RegCollpos						0x0B

#define	 RegTimerVal					0x0C
#define	 RegCRCResultLSB				0x0D
#define	 RegCRCResultMSB				0x0E
#define	 RegBitFraming					0x0F

#define	 RegTxControl					0x11
#define	 RegCWConductance				0x12
#define	 RegModConductance				0x13
#define	 RegCoderControl				0x14
#define	 RegModWidth					0x15
#define	 RegModWidthSOF					0x16
#define	 RegTypeBFraming				0x17

#define	 RegRxControl1					0x19
#define	 RegDecoderControl				0x1A
#define	 RegBitPhase	 				0x1B
#define	 RegRxThreshold 				0x1C
#define	 RegBPSKDemod	 				0x1D
#define	 RegBPSKDemControl	 			0x1D
#define	 RegRxControl2  				0x1E

#define	 RegRxWait						0x21
#define	 RegCRCSetting					0x22
//---------RC632¼Ä´æÆ÷---¼Ä´æÆ÷ÖØ¸´Òª´¦Àí-------
#define RegChannelRedundancy 			0x22
//----------------------------------------------

#define	 RegCRCPresetLSB 				0x23
#define	 RegCRCPresetMSB 				0x24

#define	 RegFIFOLevel	  				0x29
#define	 RegTimerClock					0x2A
#define	 RegTimerControl 				0x2B
#define	 RegTimerReload  				0x2C
#define	 RegManFilterCtrl				0x2E
#define	 RegFilterCorCoef				0x2F

#define	 RegIOConfig					0x31

#define	 RegSSI_FValue					0x37

#define	 RegTestAnaSel					0x3A
#define	 RegTxDisableCtrl  				0x3B
#define	 RegISO15693Header 				0x3D
#define	 RegAnalogAdjust1				0x3E
#define	 RegAnalogAdjust2				0x3F





//************** Command for SIC931 ***********************//
#define	 CMDIdle		0x00
#define	 CMDTransmit	0x1A
#define	 CMDReceive		0x16
#define	 CMDTranceive	0x1E
#define	 CMDWriteE2		0x01
#define	 CMDReadE2		0x03
#define	 CMDLoadConfig	0x07
#define	 CMDCalCRC		0x12
#define	 CMDLoadKey		0x19
#define	 CMDLoadKeyE2	0x0B
#define	 CMDAuthent 	0x1C

//******* Mask for Control Reg (Reg 0x09) ***************************//
#define	 Crypto1On_Mask			0x08
#define	 Crypto1On_Clear_Mask	0xF7
#define	 FlushFIFO_Set_Mask		0x01
#define	 TStartNow_Set_Mask		0x02
#define	 TStopNow_Set_Mask		0x04

//******* Mask for Err Reg (Reg 0x0A) *******************************//
#define	 CollErr_Mask			0x01
#define	 ParityErr_Mask			0x02
#define	 FramingErr_Mask		0x04
#define	 CRCErr_Mask			0x08
#define	 FIFOOvfl_Mask			0x10
#define	 AccessErr_Mask			0x20
#define	 KeyErr_Mask			0x40
#define	 E2Err_Mask				0x80

//******* Mask for TxControl Reg (Reg 0x11) *************************//
#define	 ModSource_Clear_Mask	0x9F
#define	 Force100ASK_Set_Mask	0x10
#define	 Force100ASK_Clear_Mask	0xEF
#define	 TX2RFEn_Set_Mask		0x02
#define	 TX2RFEn_Clear_Mask		0xFD
#define	 TX1RFEn_Set_Mask		0x01
#define	 TX1RFEn_Clear_Mask		0xFE
#define	 TX2Inv_Clear_Mask		0xF7
#define	 TX2Cw_Set_Mask			0x04
#define	 TX2Cw_Clear_Mask		0xFB

//******* Mask for CoderControl Reg (Reg 0x14) **********************//
#define	 Send1Pulse_Set_Mask	0x80
#define	 Send1Pulse_Clear_Mask	0x7F

//******* Mask for TypeBFraming Reg (Reg 0x17) **********************//
#define	 EOFWidth_Clear_Mask			0xDF
#define	 SOFWidth_Clear_Mask			0xFC
#define	 EOF_10etu_Set_Mask				0x00
#define	 EOF_11etu_Set_Mask				0x20
#define	 SOF_10etu_Add_2etu_Set_Mask	0x00
#define	 SOF_10etu_Add_3etu_Set_Mask	0x01
#define	 SOF_11etu_Add_2etu_Set_Mask	0x02
#define	 SOF_11etu_Add_3etu_Set_Mask	0x03

//******* Mask for Decoder Control Reg (Reg 0x1A) *******************//
#define	 CollMaskVal_Mask	 	0x40
#define	 CollMaskVal_Set_Mask	0x40
#define	 CollMaskVal_Clear_Mask	0xBF

//******* Mask for Decoder Control Reg (Reg 0x1A) *******************//
#define	 ZeroAfterColl_Mask	 	0x20
#define	 ZeroAfterColl_Set_Mask	        0x20
#define	 ZeroAfterColl_Clear_Mask	0xDF

//******* Mask for Decoder Control Reg (Reg 0x1A) *******************//
#define	 RxMultiple_Mask		0x80
#define	 RxMultiple_Set_Mask	        0x80
#define	 RxMultiple_Clear_Mask	        0x7F

//******* Mask for CRCSetting Reg (Reg 0x22) ************************//
#define	 TxCRCEn_Set_Mask		0x04
#define	 TxCRCEn_Clear_Mask		0xFB
#define	 RxCRCEn_Set_Mask		0x08
#define	 RxCRCEn_Clear_Mask		0xF7

//******* Mask for TimerClock Reg (Reg 0x2A) ************************//
#define	 TPreScaler_Mask		0x1F
#define	 TPreScaler_Clear_Mask	0xE0

//******* Crypto Status **********************************//
#define	 CRYPTO_NOT_ON			        0x00
#define	 CRYPTO_ON				0x01
#define	 CHECK_DISABLE				0x00
#define	 CHECK_ENABLE			        0x01

//************* Interrupt Value for SIC931 ****************//
#define	 CLEAR_ALL_IRQ_SOURCE	0x3F
#define	 ALL_IRQ_SOURCE			0x3F
#define	 TimerIRQ				0x20
#define	 TxIRQ					0x10
#define	 RxIRQ					0x08
#define	 IdleIRQ				0x04
#define	 HiAlertIRQ				0x02
#define	 LoAlertIRQ				0x01

//************* Timer Setting for SIC931 ****************//
#define	 TimerManual	0x00

#define	 TStartTxBegin	0x01
#define	 TStartTxEnd	0x02

#define	 TStopRxBegin	0x01
#define	 TStopRxEnd		0x02

//************* ModSource for SIC931 ****************//
#define	 ModSource_TriState	0x00
#define	 ModSource_High		0x01
#define	 ModSource_Internal	0x02
#define	 ModSource_SIGIN0	0x03

//************* CRC Setting for SIC931 ****************//
#define	 TxCRC_Disable	0x00
#define	 TxCRC_Enable	0x01
#define	 RxCRC_Disable	0x00
#define	 RxCRC_Enable	0x01

//************* EOF SOF Selection *********************//
#define  SOF_10etu_Add_2etu		0x00  
#define  SOF_10etu_Add_3etu		0x01
#define  SOF_11etu_Add_2etu		0x02
#define  SOF_11etu_Add_3etu		0x03

#define  EOF_10etu	0x00
#define  EOF_11etu	0x01

//************* Speed for each Standard ****************//
//--For ISO14443A, ISO14443B-------//
// Speed Tx and Rx
#define	 SPEED_106_KBPS			0x00
#define	 SPEED_212_KBPS			0x01
#define	 SPEED_424_KBPS			0x02
#define	 SPEED_848_KBPS			0x03

//---- For ISO15693----------------//
// Speed Tx
#define	 SPEED_1_OUT_OF_256		0x00
#define	 SPEED_1_OUT_OF_4		0x01
// Speed Rx
#define	 SPEED_1_SUB_LOW		0x00
#define	 SPEED_1_SUB_HIGH		0x01
#define	 SPEED_1_SUB_ULTRA_HIGH	0x02
#define	 SPEED_2_SUB_LOW		0x03
#define	 SPEED_2_SUB_HIGH		0x04

//---- ForFelica---------------//
// Speed Tx and Rx
#define	 SPEED_FELICA_212_KBPS		0x00
#define	 SPEED_FELICA_424_KBPS		0x01

//---- Move from SIC931_Board_Define.h --//
#define DATA_RF_BUFFER_SIZE			512 
#define DATA_BUFFER_SIZE			512 
#define PACKAGE_BUFFER_SIZE			512 + 9 // (Header(1 byte) + Len_H(1) + Len_L(1) + Sequence_Num(1) + Dev_ID(1) + Cmd_Category(1) + Sub_Cmd(1) + Resp(1) + Data(512) + LRC(1))
#define SIC931BOARD_BUFFER_SIZE		512

#define	_SUCCESS_					0x01 // Operation success


#define DRIVER_CONFIG_X_CC		0x00 // Diffential Close Coupling Network with internal envelope
#define DRIVER_CONFIG_X_CCXENV		0x01 // Diffential Close Coupling Network with external envelope
#define DRIVER_CONFIG_X_S50OUT		0x02 // Single-ended Drive with external envelope
#define DRIVER_CONFIG_X_E50OUT		0x03 // 50 ohm output from Class-E driver with external envelope 


// --- RF Communication Err ---//
#define NO_RESPONSE				0xE0 // No card response within given time indicating by timeout from ASIC Timer
#define FRAMING_ERR				0xE1 // Format of receive frame errors indicating by FramingErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)										
#define COLLISION_ERR				0xE2 // Bit collision is detected indicating by CollErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)											
#define PARITY_ERR				0xE3 // Parity Bit Check is invalid indicating by ParityErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)											
#define CRC_ERR					0xE4 // CRC Check is invalid indicating by CRCErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)											
#define INVALID_RESP				0xE5 // Response is invalid or unexpected from operation protocol
#define SUBC_DET_ERR    			0xE6 // Subcarrier from card is detected indicating by SubC_Det bit in SIC9410's Status register (Reg 0x05)	
                                                     // but can not recoginzed following standard (available only SIC9410)
//-- Reader Chip(SIC931) System Err --//
#define BUFFER_OVERFLOW_ERR			0xF0 // SIC9xx's FIFO overflow indicating by FIFOOvlf bit in SIC9xx's ErrorFlag register (Reg 0x0A)	
#define ACCESS_E2_ERR				0xF1 // Accessing EEPROM error indicating by AccessErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)	
#define WRITE_E2_ERR				0xF2 // Writing EEPROM error indicating by E2Err bit in SIC9xx's ErrorFlag register (Reg 0x0A)	
#define KEY_ERR					0xF3 // Loaded Key is in invalid format indicating by KeyErr bit in SIC9xx's ErrorFlag register (Reg 0x0A)	 
#define ASIC_EXE_TIMEOUT			0xF4 // No ASIC response within given time indicating by timeout from MCU Timer
#define SIC931_DIAGNOSE_ERR			0xF5 

// ISO14443A Err
#define A_HALT_ERR					0xA0 // Error if there is a response after sending Halt command 
#define AUTHENT_ERR					0xA1 // Error if Crypto1 bit in Control register(Reg 0x09) is not set after performing AUTHENT command 
#define NOT_AUTHENT					0xA2 // Error from Operating MIFARE command i.e. Increment when crypto1 bit is not set
#define MIFARE_ERR					0xA3 // NACK (0x04 or 0x05) from MIFARE card is received


#endif

